Design and Implementation of a High-Performance RISC-V CPU IP Core for Multiple Cryptographic Algorithms
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Abstract
To satisfy the low-overhead and high-throughput requirements of embedded computing platforms executing cryptographic workloads, this study presents a high-performance RISC-V CPU IP core compatible with the standard RV32IM architecture. Instead of introducing dedicated cryptographic instructions, the proposed design enhances the execution efficiency of algorithms such as SM3 and SM4 through microarchitectural optimization of arithmetic units. A hierarchical multiplier architecture consisting of partial-product generation, 4–2 compressor-tree reduction, and a look-ahead adder is developed to improve multiplication throughput, while an enhanced radix-4 SRT divider incorporating leading-zero detection, result caching, and dynamic iteration control is proposed to reduce division latency. All modules are implemented in Verilog and integrated into a five-stage RISC-V pipeline. Functional verification is performed using a complete RVM instruction test suite, followed by FPGA-based performance evaluation. Experimental results demonstrate that the multiplier generates 64-bit results within a single clock cycle in 32-bit scenarios, reducing latency by more than 70% compared with conventional Wallace-tree implementations. The proposed architecture provides an efficient computing platform for secure embedded systems and offers implementation references for real-time signal processing, communication security, and electromagnetic information systems.
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References
S. Di Mascio, A. Menicucci, E. Gill, et al., “Leveraging the Openness and Modularity of RISC-V in Space,” Journal of Aerospace Information Systems, vol. 16, no. 11, pp. 454–472, 2019, doi: 10.2514/1.I010735.
A. Kamaleldin, S. Hesham, and D. Göhringer, “Towards a modular RISC-V based many-core architecture for FPGA accelerators,” IEEE Access, vol. 8, pp. 148812–148826, 2020, doi: 10.1109/ACCESS.2020.3015706.
V. A. Frolov, V. A. Galaktionov, and V. V. Sanzharov, “Investigation of RISC-V,” Programming and Computer Software, vol. 47, no. 7, pp. 493– 504, 2021, doi: 10.1134/S0361768821070045.
A. Dörflinger, M. Albers, B. Kleinbeck, et al., “A comparative survey of open-source application-class RISC-V processor implementations,” in Proceedings of the 18th ACM International Conference on Computing Frontiers, 2021, pp. 12–20, doi: 10.1145/3457388.3458657.
S. Kalapothas, M. Galetakis, G. Flamis, et al., “A survey on risc-v-based machine learning ecosystem,” Information, vol. 14, no. 2, p. 64, 2023, doi: 10.3390/info14020064.
V. Herdt and R. Drechsler, “Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges,” Science China Information Sciences, vol. 65, no. 1, p. 110201, 2022, doi: 10.1007/s11432-020-3308-4.
J. Qu, H. Liu, R. Zhang, and L. Wen, “Design of a divider with the improved pre-processing module based on SRT-4 algorithm,” in International Conference on Electronic Materials and Information Engineering (EMIE 2023), Art. no. 4, 2023, doi: 10.1117/12.3010604.
B. Mehta, J. Talukdar, and S. Gajjar, “High speed SRT divider for intelligent embedded system,” in 2017 International Conference on Soft Computing and its Engineering Applications (icSoftComp), pp. 1-5, 2017, doi: 10.1109/icsoftcomp.2017.8280077.
X. Zheng, X. Hu, J. Zhang, et al., “An efficient and low-power design of the SM3 hash algorithm for IoT,” Electronics, vol. 8, no. 9, p. 1033, 2019, doi: 10.3390/electronics8091033.
H. J. Lu, R. A. Juanatas, and M. B. Abisado, “Enhancing security in instant messaging systems with a hybrid SM2, SM3, and SM4 encryption framework,” PLoS One, vol. 20, no. 9, p. e0332665, 2025, doi: 10.1371/journal.pone.0332665.
S. Sun, R. Zhang, and H. Ma, “Hashing multiple messages with SM3 on GPU platforms,” Science China Information Sciences, vol. 64, no. 9, p. 199103, 2021, doi: 10.1007/s11432-018-9648-x.
J. Chen and F. You, “An image encryption algorithm based on SM4 and Base64,” Journal of Physics: Conference Series, vol. 1812, no. 1, p. 012041, 2021, doi: 10.1088/1742-6596/1812/1/012041.
S. E. Abed, R. Jaffal, B. J. Mohd, and M. Alshayeji, “Performance evaluation of the SM4 cipher based on field‐programmable gate array implementation,” IET Circuits, Devices & Systems, vol. 15, no. 2, pp. 121-135, 2021, doi: 10.1049/cds2.12011.
X. Hu, H. Yi, W. Zhang, et al., “Optimizing the SM4 Encryption Algorithm for Blockchain Security,” in CCF China Blockchain Conference, Singapore: Springer Nature Singapore, 2023, pp. 31–45, doi: 10.1007/978-981-99-7743-7_3.
S. Heron, “Advanced encryption standard (AES),” Network Security, vol. 2009, no. 12, pp. 8–12, 2009, doi: 10.1016/S1353-4858(10)70006-4.
B. Sarkar, A. Saha, D. Dutta, et al., “A survey on the advanced encryption standard (AES): a pillar of modern security,” Applied Sciences, vol. 14, no. 18, p. 8395, 2024, doi: 10.47760/ijcsmc.2024.v13i04.008.
Y. Shi, Y. Cheng, L. Cui, et al., “Research on System Data Security Based on State Secret Algorithm,” in 2024 IEEE 6th International Conference on Power, Intelligent Computing and Systems (ICPICS), IEEE, 2024, pp. 701–705, doi: 10.1109/icpics62053.2024.10796842.
X. Xing, S. Li, R. An, et al., “A Data Migration Scheme Based on State Secret Algorithm,” in 2025 Asia-Europe Conference on Cybersecurity, Internet of Things and Soft Computing (CITSC), IEEE, 2025, pp. 259– 261, doi: 10.1109/citsc64390.2025.00053.