Power Prediction Modelling for CPU–GPU Heterogeneous Platforms Based on Heterogeneous Feature Sequence Modelling

Main Article Content

J. W. Hu

Abstract

Central processing unit-graphics processing unit (CPU-GPU) heterogeneous platforms are widely deployed for AI-related, data-processing, and compute-intensive workloads. Their practical deployment is constrained by fluctuating node power, cross-device coordination overhead, and uneven energy efficiency. This paper develops a Transformer, a convolutional neural network, and a long short-term memory (LSTM) architecture (Transformer-CNN-LSTM) for system-level power prediction. Runtime features are cleaned, normalised, and reorganised into sliding-window sequences, allowing the model to learn global feature interactions, local workload fluctuations, and temporal evolution within a single prediction pipeline. Experiments on the collected CPU-GPU dataset demonstrate that this method achieves better results than CNN and LSTM, CNN-LSTM, performance monitoring counter statistical (PMC-Stat), and GPUWattch-Inspired baselines. The model achieves mean square error (MSE), root mean square error (RMSE), mean absolute error (MAE), and R2 results of 50.31, 7.09, 4.79, and 0.98, respectively, indicating its potential for runtime power estimation and energy-aware platform management.

Downloads

Download data is not yet available.

Article Details

How to Cite
Hu, J. W. (2026). Power Prediction Modelling for CPU–GPU Heterogeneous Platforms Based on Heterogeneous Feature Sequence Modelling. Advanced Electromagnetics, 15(3), 10531–10542. https://doi.org/10.7716/aem.v15i3.4258
Section
Research Articles

References

S. Mittal and J. S. Vetter, “A survey of CPU-GPU heterogeneous computing techniques,” ACM Comput. Surv., vol. 47, no. 4, p. 69, 2015.

K. O’Brien, I. Pietri, R. Reddy, et al., “A survey of power and energy predictive models in HPC systems and applications,” ACM Comput. Surv., vol. 50, no. 3, p. 37, 2017.

R. A. Bridges, N. Imam, and T. M. Mintz, “Understanding GPU power: A survey of profiling, modeling, and simulation methods,” ACM Comput. Surv., vol. 49, no. 3, p. 41, 2016.

S. Mittal and J. S. Vetter, “A survey of methods for analysing and improving GPU energy efficiency,” ACM Comput. Surv., vol. 47, no. 2, p. 19, 2013.

S. Dey, S. Isuwa, S. Saha, et al., “CPU-GPU-memory DVFS for power-efficient MPSoC in mobile cyber physical systems,” Future Internet, vol. 14, no. 3, p. 91, 2022.

K. Raju and N. N. Chiplunkar, “A survey on techniques for cooperative CPU-GPU computing,” Sustain. Comput.: Inform. Syst., vol. 19, pp. 72– 85, 2018.

J. Shen, A. L. Varbanescu, Y. Lu, et al., “Workload partitioning for accelerating applications on heterogeneous platforms,” IEEE Trans. Parallel Distrib. Syst., vol. 27, no. 9, pp. 2766–2780, 2016.

S. Hong and H. Kim, “An integrated GPU power and performance model,” in Proc. 37th Annu. Int. Symp. Comput. Archit., 2010, pp. 280–289.

H. Nagasaka, N. Maruyama, A. Nukada, et al., “Statistical power modeling of GPU kernels using performance counters,” in Proc. Int. Conf. Green Comput., 2010, pp. 115–122.

J. Lim, N. B. Lakshminarayana, H. Kim, et al., “Power modeling for GPU architectures using McPAT,” ACM Trans. Des. Autom. Electron. Syst., vol. 19, no. 3, p. 26, 2014.

J. Leng, T. Hetherington, A. Eltantawy, et al., “GPUWattch: Enabling energy optimisations in GPGPUs,” in Proc. 40th Annu. Int. Symp. Comput. Archit., 2013, pp. 487–498.

V. Kandiah, S. Peverelle, M. Khairy, et al., “AccelWattch: A power modeling framework for modern GPUs,” in Proc. MICRO-54: 54th Annu. IEEE/ACM Int. Symp. Microarch., 2021, pp. 738–753.

S. Mazzola, S. Ara, T. Benz, et al., “Data-driven power modeling and monitoring via hardware performance counter tracking,” J. Syst. Archit., vol. 167, p. 103504, 2025.

A. Shahid, M. Fahad, R. R. Manumachu, et al., “A comparative study of techniques for energy predictive modeling using performance monitoring counters on modern multicore CPUs,” IEEE Access, vol. 8, pp. 143306– 143332, 2020.

R. Bertran, Y. Becerra, D. Carrera, et al., “Energy accounting for shared virtualised environments under DVFS using PMC-based power models,” Future Gener. Comput. Syst., vol. 28, no. 2, pp. 457–468, 2012.

Z. Wang, L. Zheng, Q. Chen, et al., “CPU+GPU scheduling with asymptotic profiling,” Parallel Comput., vol. 40, no. 2, pp. 107–115, 2014.

Y. Wen, Z. Wang, and M. F. P. O’Boyle, “Smart multi-task scheduling for OpenCL programs on CPU/GPU heterogeneous platforms,” in Proc. 21st Int. Conf. High Perform. Comput., 2014, pp. 1–10.

M. N. L. Carvalho, A. Simitsis, A. Queralt, et al., “Workload placement on heterogeneous CPU-GPU systems,” Proc. VLDB Endow., vol. 17, no. 12, pp. 4241–4244, 2024.

S. Li, J. H. Ahn, R. D. Strong, et al., “McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures,” in Proc. 42nd Annu. IEEE/ACM Int. Symp. Microarch., 2009, pp. 469–480.

X. Mei, Q. Wang, and X. Chu, “A survey and measurement study of GPU DVFS on energy conservation,” Digit. Commun. Netw., vol. 3, no. 2, pp. 89–100, 2017.

H. Wang and Y. Cao, “Predicting power consumption of GPUs with fuzzy wavelet neural networks,” Parallel Comput., vol. 44, pp. 18–36, 2015.

A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low-power CMOS digital design,” IEEE J. Solid-State Circuits, vol. 27, no. 4, pp. 473–484, 1992.

K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits,” Proc. IEEE, vol. 91, no. 2, pp. 305–327, 2003.

S. Borkar, “Design challenges of technology scaling,” IEEE Micro, vol. 19, no. 4, pp. 23–29, 1999.

V. J. Hodge and J. Austin, “A survey of outlier detection methodologies,” Artif. Intell. Rev., vol. 22, no. 2, pp. 85–126, 2004.

J. M. Jerez, I. Molina, P. J. Garcia-Laencina, et al., “Missing data imputation using statistical and machine learning methods in a real breast cancer problem,” Artif. Intell. Med., vol. 50, no. 2, pp. 105–115, 2010.

K. M. Sujon, R. Hassan, Z. T. Towshi, et al., “When to use standardisation and normalisation: Empirical evidence from machine learning models and XAI,” IEEE Access, vol. 12, pp. 135300–135314, 2024.

A. Vaswani, N. Shazeer, N. Parmar, et al., “Attention is all you need,” in Adv. Neural Inf. Process. Syst. 30, 2017, pp. 5998–6008.

J. L. Ba, J. R. Kiros, and G. E. Hinton, “Layer normalisation,” arXiv:1607.06450, 2016.

Y. LeCun, L. Bottou, Y. Bengio, et al., “Gradient-based learning applied to document recognition,” Proc. IEEE, vol. 86, no. 11, pp. 2278–2324, 1998.

S. Ioffe and C. Szegedy, “Batch normalisation: Accelerating deep network training by reducing internal covariate shift,” in Proc. 32nd Int. Conf. Mach. Learn., 2015, pp. 448–456.

N. Srivastava, G. Hinton, A. Krizhevsky, et al., “Dropout: A simple way to prevent neural networks from overfitting,” J. Mach. Learn. Res., vol. 15, no. 56, pp. 1929–1958, 2014.

D. P. Kingma and J. Ba, “Adam: A method for stochastic optimisation,” arXiv:1412.6980, 2014.

S. Hochreiter and J. Schmidhuber, “Long short-term memory,” Neural Comput., vol. 9, no. 8, pp. 1735–1780, 1997.