Assessment of 50%-Propagation-Delay for Cascaded PCB Non-Linear Interconnect Lines for the High-Rate Signal Integrity Analysis

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T. Eudes
B. Ravelo
R. Al-Hayek


This paper presents an enlarged study about the 50-% propagation-time assessment of cascaded transmission lines (TLs). First and foremost, the accurate modeling and measurement technique of signal integrity (SI) for high-rate microelectronic interconnection is recalled. This model is based on the reduced transfer function extracted from the electromagnetic (EM) behavior of the interconnect line RLCG-parameters. So, the transfer function established takes into account both the frequency dispersion effects and the different propagation modes. In addition, the transfer function includes also the load and source impedance effects. Then, the SI analysis is proposed for high-speed digital signals through the developed model. To validate the model understudy, a prototype of microstrip interconnection with w = 500 µm and length d = 33 mm was designed, simulated, fabricated and tested. Then, comparisons between the frequency and time domain results from the model and from measurements are performed. As expected, good agreement between the S-parameters form measurements and the model proposed is obtained from DC to 8 GHz. Furthermore, a de-embedding method enabling to cancel out the connectors and the probe effects are also presented. In addition, an innovative time-domain characterization is proposed in order to validate the concept with a 2.38 Gbit/s-input data signal. Afterwards, the 50-% propagation-time assessment problem is clearly exposed. Consequently an extracting theory of this propagation-time with first order RC-circuits is presented. Finally, to show the relevance of this calculation, propagation-time simulations and an application to signal integrity issues are offered.


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Eudes, T., Ravelo, B., & Al-Hayek, R. (2013). Assessment of 50%-Propagation-Delay for Cascaded PCB Non-Linear Interconnect Lines for the High-Rate Signal Integrity Analysis. Advanced Electromagnetics, 2(1), 1–14.
Research Articles


International Technology Roadmap for Semiconductors Update Overview, 2011. Available at: http://www.itrs.

B. Bottom, "Assembly and Packaging White Paper on System Level Integration," ITRS white papers, 2009. Available at:

F. Jun, Y. Xiaoning, J. Kim, B. Archambeault, and A. Orlandi, "Signal Integrity Design for High-Speed Digital Circuits: Progress and Directions," IEEE Trans. EMC, Vol. 52, No. 2, pp. 392-400, May 2010.

J. F. Buckwalter, "Predicting Microwave Digital Signal Integrity," IEEE Trans. Advanced Packaging, Vol. 32, No. 2, pp. 280-289, May 2009.

View Article

J. Kim, and E. Li, "Special Issue on PCB Level Signal Integrity, Power Integrity, and EMC," IEEE Trans. EMC, Vol. 52, No. 2, pp. 246-247, May 2010.

E. Bogatin, "Essential Principles of Signal Integrity," IEEE Microwave Magazine, Vol. 12, No. 5, Aug. 2011.

View Article

Y. I. Ismail, and E. G. Friedman, "Effects of Inductance on the Propagation, Delay and Repeater Insertion in VLSI Circuits", IEEE Trans. VLSI Systems, Vol. 8, No. 2, pp. 195-206, Apr. 2000.

View Article

A. Deutsch, G.V . Kopcsay, P. Restle, G. Katopis, W. D. Becker, H. Smith, P. W. Coteus, C. W. Surovic, B. J. Rubin, R. P. Dunne, T. Gallo, K. A. Jenkins, L. M. Terman, R. H. Dennard, G. A. Sai-Halasz, and D. R. Knebel, "When are transmission-line effects important for on-chip interconnection", IEEE Trans. MTT, Vol. 45, No. 10, pp. 1836-1846, Oct. 1997.

View Article

M. Celik, L. Pileggi, and A. Odabasioglu, IC Interconnect Analysis, Kluwer Academic Publisher, Dordrecht, Germany, 2002.

M. Zolog, and D. Piticã, "Controlling the Signal Integrity through the Geometry of the Microstrip on the Digital PCBs," Electronic System-Integration Technology Conference (ESTC), Berlin, Germany, Sep. 2010.

View Article

F. W. L. Kung and H. T. Chuah, "System Modeling of High-Speed Digital Printed Circuit Board Using SPICE," Progress In Electromagnetics Research, Vol. 20, pp. 179-211, 1998.

View Article

T. Granberg, "Handbook of Digital Techniques for High Speed Design," Pentrice Hall Modern Semiconductor Design Series, Ed. by Pentrice Hall, Chapter 1, pp. 3-16, 2004.

T. Eudes, B. Ravelo, and A. Louis, "Transient Response Characterization of the High-Speed Interconnection RLCG Model for the Signal Integrity Analysis," PIER J., Vol. 112, 183-197, Jan. 2011.

T. Eudes, B. Ravelo, and A. Louis, "Experimental validations of a simple PCB interconnect model for high-rate signal integrity," To be published in IEEE Trans. EMC, pp. 1-8, Sept. 2011.

View Article

G. L. Matthaei, L Young, and E. M. T. Jones, Microwave Filters, Impedance Matching and Coupling Structures, Artech House Microwave Library, Norwood, MA, Ed. by Artech House, 1980.

P. G. Huray, The Foundations of the Signal Integrity, Ed. by Wiley and Sons Inc., Hoboken, NJ, 2010.

J. Cho, E. Song, H. Kim, S. Ahn, J. S. Pak, Ji. Kim and Jo. Kim "Mixed-Mode ABCD Parameters: Theory and Application to Signal Integrity Analysis of PCB-Level Differential Interconnects," IEEE Trans. EMC, Vol. 53, No. 3, pp.1-9, Aug. 2011.

J. H. Kim, D. Oh, and W. Kim, "Accurate Characterization of broadband Multiconductor Transmission Lines for High-Speed Digital Systems," IEEE Trans. Advanced Packaging, Vol. 33, No. 4, pp. 857-867, Nov. 2010.

View Article

A. Koul, P. K. R. Anmula, M. Y. Koledintseva, J. L. Drewniak and S. Hinaga, "Improved Technique for Extracting Parameters of Low-Loss Dielectrics on Printed Circuit Boards," in Proc. of IEEE EMC Symp., pp. 191-196, Aug. 2009.

K. S. R. Krishna, J. L. Narayana and L. P. Reddy, "ANN Models for Microstrip Line Synthesis and Analysis," Int. J. Elect. Syst. Sci. Eng., Vol. 1, pp.196-200, 2008.

J. Lilja, R. Mäkinen, V. Pynttäri, P. Mansikkamäki, and M. Kivikoski, "Application of Thin-Film RCLG Model for the Modeling of Inkjet Printed Microstrip Lines", in Proc. of 12th Workshop on SPI, pp. 1-4, May 2008.

Y. Shlepnev, "Modeling Frequency-Dependent Conductor Losses and Dispersion in Serial Data Channel Interconnects," Simberian Inc., 2007. Available at:

M. Resso, and E. Bogatin, Signal Integrity Characterization Techniques, Int. Engineering Consortium, Ed. by IEC Publications, 2009.

N. Nakhla, M. Nakhla, and R. Achar, "A General Approach for Sensitivity Analysis of Distributed Interconnects in the Time Domain," IEEE Trans. MTT, Vol. 59, No. 1, pp. 46-55, Jan. 2011.

View Article

S. Roy, and A. Dounavis, "RLC Interconnect Modeling using Delay Algebraic Equations," in Proc. of IEEE CAS Workshop, Dallas, CO, Oct. 2009.

S. Gupta, A. Parsa, E. Perret, R. V. Snyder, R. J. Wenzel and C. Caloz, "Group-Delay Engineered Noncommensurate Transmission Line All-Pass Network for Analog Signal Processing," IEEE Trans. MTT, Vol. 58, No. 9, pp. 2392-2407, Sept. 2010.

View Article

J. L. Naredo, J. A. Gutérrez, F. A. Uribe, J. L. Guardado and V. H. Ortiz, "Frequency Domain Methods for Electromagnetic Transient Analysis," in Proc. of IEEE Power Engineering General Meeting, pp. 1-7, June 2007.

P. Wittwer and P. J. Pupalaikis, "A general Closed-Form Solution to Multi-Port Scattering Parameter Calculations," in Proc. of the 72nd ARFTG Microwave. Meas. Symp., pp. 137-143, Dec. 2008.

D. A. Frickey, "Conversions Between S, Z, Y, h, ABCD and T Parameters which are Valid for Complex Source and Load Impedances," IEEE Trans. MTT, Vol. 42, No. 2, pp. 205-216, Feb. 1994.

View Article

B. Ravelo and T. Eudes, "Fast estimation of RL-loaded microelectronic interconnections delay for the signal integrity prediction," To be published in Int. J. Numer. Model.

View Article

V. Adler, E. G. Friedman, "Repeater Design to Reduce Delay and Power in Resistive Interconnect," IEEE Trans. on CAS II, Vol. 45, No. 5, May 1998.

B. Ravelo, A. Perennec, and M. Le Roy, "New Technique of Inter-Chip Interconnect Effects Equalization with Negative Group Delay Active Circuits", VLSI, Chap. 20, INTECH Book, Ed. by Z. Wang, 409-434, Feb. 2010.

B. Ravelo, A. Perennec, and M. Le Roy, "Experimental Validation of the RC-Interconnect Effect Equalization with Negative Group Delay Active Circuit in Planar Hybrid Technology," in Proc. of 13th IEEE Workshop SPI, Strasbourg, France, May 2009.

B. Ravelo, A. Pérennec, M. Le Roy, and Y. Boucher, "Active Microwave Circuit with Negative Group Delay," IEEE MWC Lett., Vol. 17, No. 12, pp. 861-863, Dec. 2007.

T. Eudes and B. Ravelo, "Cancellation of Delays in the High-Rate Interconnects with UWB NGD Active Cells," Applied Physics Research, Vol. 3, No. 2, Nov. 2011.

J. Cong, L. He, C.K. Koh, and P.H. Madden, "Performance Optimization of VLSI Interconnect Layout," Integration VLSI J., Vol. 21, No. 1-2, Nov. 1996, pp. 1-94.

View Article

L. Xiao-Chun, M. Jun-Fa, and T. Min, "High-speed Clock Tree Simulation Method Based on Moment Matching," in 2005 Proc. PIERS, Hangzhou (China), Vol. 1, No. 2, pp. 142-146.

L. Hungwen, S. Chauchin and L. J. Chien-Nan, "A Tree-Topology Multiplexer for Multiphase Clock System," IEEE Tran. CAS I, Vol. 56, No. 1, Feb. 2009, pp. 124-131.

N. Rakuljic and I. Galton, "Tree-Structured DEM DACs with Arbitrary Numbers of Levels," IEEE Tran. CAS I, Vol. 52, No. 2, Feb. 2010, pp. 313-322.

G. F. Bo and P. Ampadu, "On Hamming Product Codes With Type-II Hybrid ARQ for On-Chip Interconnects," IEEE Tran. CAS I, Vol. 56, No. 9, Sep. 2009, pp. 2042-2054.

M. Voutilainen, M. Rouvala, P. Kotiranta and T. Rauner, "Multi-Gigabit Serial Link Emissions and Mobile Terminal Antenna Interference," 13th IEEE Workshop on SPI, Strasbourg (France), May 2009.

W. C. Elmore, "The transient response of damped linear networks," J. Appl. Phys., Vol. 19, Jan. 1948, pp. 55-63.

View Article

L. Wyatt, "Circuit Analysis, Simulation and Design. North-Holland," The Netherlands : Elsiever Science, 1978.

Jr. P. Penfield and J. Rubinstein, "Signal delay in RC tree networks," in 1981 Proc. of Caltech Conf. on VLSI, pp. 269-283.

J. Rubinstein, Jr. P. Penfield, and M. A. Horowitz, "Signal delay in RC tree networks," IEEE Trans. CAD, Vol. 2, No. 3, Jul. 1983, pp. 202-211.

C. A. Zukowski, "Relaxing bounds for linear RC mesh circuits," IEEE Trans. CAD, Vol. 5, Apr. 1986, pp. 305-312.

P. K. Chan and M. D. F. Schlag, "Bounds on Signal Delay in RC Mesh Networks," IEEE Trans. CAD, Vol. 8, Jun. 1989, pp. 581-589.

M. A. Horowitz, "Timing Models for MOS Pass Networks," in 1983 Proc of IEEE ISCAS, pp. 198-201.

Jr. J. L. Wyatt, "Signal Delay in RC Mesh Networks," IEEE Tran. CAS, Vol. 32, No. 5, May 1985, pp. 507-510.

Jr. J. L. Wyatt, "Signal Propagation Delay in RC Models for Interconnect," Circuit Analysis, Simulation and Design, Part II: VLSI Circuit Analysis and Simulation, A. Ruchli, ed., Vol. 3 in the series Advances in CAD for VLSI, North-Holland, 1987.

N. K. Jain, V. C. Prasad and A. B. Bhattacharyyaa, "Delay-Time Sensitivity in Linear RC Tree," IEEE Trans. CAS, Vol. 34, No. 4, 1987, pp. 443-445.

View Article

A. C. Deng and Y. C. Shiau, "Generic Linear RC Delay Modeling for Digital CMOS Circuits," IEEE Tran. CAD, Vol. 9, No. 4, Apr. 1990, pp. 367-376.

R. Gupta, B. Tutuianu and L. T. Pileggi, "The Elmore delay as a bound for RC trees with generalized input signals," IEEE Tran. CAD, Vol. 16, No. 1, 1997, pp. 95-104.

Y. I. Ismail, E. G. Friedman and J. L. Neves, "Equivalent Elmore Delay for RLC Trees", IEEE Tran. CAD, Vol. 19, No. 1, Jan. 2000, pp. 83-97.

F. R. Awwad, M. Nekili, V. Ramachandran and M. Sawan, "On Modeling of Parallel Repeater-Insertion Methodologies for SoC Interconnects," IEEE Tran. CAS I, Vol. 55, No. 1, Feb. 2008, pp. 322-335.

A. B. Kahng, and S. Muddu, "An Analytical Delay model of RLC interconnects," IEEE Trans. CAD, Vol. 16, Dec. 1997, pp. 1507-1514.

A. Ligocka and W. Bandurski, "Effect of Inductance on Interconnect Propagation Delay in VLSI Circuits", in Proc. of 8th Workshop on SPI, 9-12 May 2004, pp. 121-124.

W. Maichen, "When Digital Becomes Analog-Interfaces in High Speed Test," Proc. 12th IEEE Workshop on SPI, Avignon (France), May 2008.

J. A. Charles, F. Liu, C. V. Kashyap and A. Devgan, "Closed-Form Delay and Slew Metrics Made Easy," IEEE Tran. CADICAS I, Vol. 23, No. 12, Dec. 2004, pp. 1661-1669.

C. V. Kashyap, C. J. Alpert, F. Liu and A. Devgan, "Closed-Form Expressions for Extending Step Delay and Slew Metrics to Ramp Inputs for RC Trees," IEEE Tran. CADICAS I, Vol. 23, No. 4, Apr. 2004, pp. 509-516.

C. J. Alpert, F. Liu, C. Kashyap, and A. Devgan, "Delay and Slew Metrics Using the Lognormal Distribution," In Proc. of the 40th annual Design Automation Conf., 2003, pp. 382-385.

A. Blankman, "De-embedding Gigaprobes® Using Time Domain Gating with the LeCroy SPARQ," LeCroy SPARQ Application Note. Available at:

A. Blankman, "LeCroy SPARQ S-Parameter Measurement and Methodology," LeCroy Technical Brief, Rev. 3, July 2011. Available at:

A. Blankman, "SPARQ S-Parameter Measurements with Impulse Response Time Limiting," LeCroy.

Technical Note, Rev. 2, June 2011. Available at:

P. J. Pupalaikis, "SPARQ Dynamic Range," LeCroy Technical Brief. Available at:

M. Schnecker, M. Miller and J. Schachner, "Signal Integrity Measurement in High Bit Rate Systems," Presented at DesignCon2009, Santa Clara, CA, US, Feb. 2009. J. Kenney and P. J. Pupalaikis, "Timing Measurement Problems and Solutions in Source Terminated Memory Systems with Inaccessible Probing Points," in Proc. of DesignCon2010, Santa Clara, CA, US, Feb. 2010.

P. J. Pupalaikis, "Wavelet Denoising for TDR Dynamic Range Improvement," in Proc. of DesignCon2011, Santa Clara, CA, US, Feb. 2011. "240-Pin PC-6400/PC-5300/PC-4200/PC-3200 DDR2 SDRAM Registered DIMM Design Specification," JEDEC Standard, No. 21C, Rev. 4.04, Jan. 2010. Available at:

T. Eudes, B. Ravelo and R. Al Hayek, "Fast and Accurate Modeling of PCB Interconnection Lines for High-Rate Signal Integrity Analysis," (Accepted for communication) Proc. of AES 2012, Paris, Apr. 2012.

B. Ravelo, "Time-domain analysis of microwave pulse compression with NGD circuit", To be published in International Journal of Communication Engineering Applications (IJCEA), IJCEA-TJ-04-68, 2012.